Design Verification Engineer, Annapurna Labs
Core
Design Verification Engineer developing comprehensive verification solutions for high-speed I/O and scale-up/out components across the SoC in AWS custom ML accelerators (Inferentia, Trainium).
Role type
Senior IC design verification engineer
Builds
Custom machine learning data center accelerator chips (AWS Inferentia, Trainium)
Domain
Semiconductor / Custom Silicon / Machine Learning Infrastructure
Deliverable
production ML models
Required skills
constrained-random simulation (UVM), system-level verification, IP block to SoC verification, debugging architecture and algorithms, test scenario creation, coverage closure
Preferred skills
Python or Perl scripting, C/C++ and OOP, AMBA protocols (AHB/APB/AXI), interconnect protocols (PCIe, UCIe)
Technologies
UVM, PCIe, UCIe, AMBA
Responsibilities
Own development and execution of verification plans for sub-system and chip levels; Build and implement verification environments using advanced simulation methodologies; Define and execute comprehensive test scenarios covering system-level flows and corner cases; Drive coverage closure and verification sign-off
Seniority
Senior, hands-on IC
