Sr. SDE, MLA hardware/software co-design, Annapurna Labs Machine Learning Acceleration
Core
Pre-silicon hardware/software co-development and verification for next-generation AI chips (Trainium).
Role type
Senior IC SDE (Hardware/Software Co-design)
Builds
Custom machine learning chips (ASIC/FPGA)
Domain
Cloud infrastructure / AI hardware acceleration
Deliverable
production ML models
Required skills
C/C++, Bash/Python, data structures and algorithms, HW/SW interfaces, computer architecture
Preferred skills
RTL coding and debug, performance/power/area analysis, ASIC/FPGA design tools, SoC bring-up
Technologies
C, C++, Bash, Python, RTL, ASIC, FPGA, SoC
Responsibilities
Build and test next generation AI chips with architecture and design teams; Write bare-metal software and ML workloads to verify end-to-end functionality and performance of the SoC.
Seniority
Senior, hands-on IC
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