Staff Verification Engineer- LoRa
Core
Define and implement test plans, develop assertion-based checkers, and perform functional verification of RTL designs using UVM methodologies to ensure completeness and quality of SoC designs.
Role type
Staff IC verification engineer (SoC/RTL)
Builds
Production-ready SoC designs and RTL blocks
Domain
Semiconductor hardware design and verification
Deliverable
production ML models | product features | dashboards & analysis | research | client delivery | infrastructure | physical/clinical work -> infrastructure (RTL verification)
Required skills
SystemVerilog, UVM, assertion-based verification, coverage-driven verification, formal verification, debugging RTL, bus architecture verification (AMBA AHB/AXI, NoC), low-power verification
Preferred skills
Python, Tcl, Perl, Git, wireless SoC design
Technologies
VCS, QuestaSim, UVM, SystemVerilog, Python, Tcl, Perl, Git, AMBA AHB/AXI, NoC
Responsibilities
Define and implement test plans and verification strategies; Develop assertion-based checkers and functional coverage models; Perform functional verification of RTL designs; Generate and analyse coverage reports; Identify, debug, and resolve verification issues and design bugs
Seniority
Staff, hands-on IC
