Lead Solutions Engineer
Core
Develop constrained random verification environments, test plans, and coverage strategies for System on Chip (SoC) verification.
Role type
Lead Solutions Engineer (Functional Verification)
Builds
Verification environments and test components for semiconductor SoCs
Domain
Semiconductor / Hardware Verification
Deliverable
production ML models | product features | dashboards & analysis | research | client delivery | infrastructure | physical/clinical work
Required skills
System Verilog, UVM, Verilog, VHDL, C, C++, Perl, Python, AMBA protocols (AXI/AHB/APB), SoC verification, version control, load sharing software
Preferred skills
Cadence tools and flows, ARM/CPU architectures, assembly language programming, embedded C development, formal verification, additional protocols (UART, I2C, SPI, JTAG)
Technologies
System Verilog, UVM, Verilog, VHDL, C, C++, Perl, Python, AMBA, ARM, Cadence
Responsibilities
Review design specifications and develop verification strategies, create constrained random verification environments, write test sequences and functional coverage assertions, develop C-based test cases for SoC verification
Seniority
Senior, hands-on IC
