Senior / Staff Design Verification Engineer
Core
Ensure functional correctness of complex, next-generation SoCs/IPs through the entire verification lifecycle from test plan creation to 100% coverage closure.
Role type
Senior IC design verification engineer (ASIC/SoC)
Builds
Tape-out-ready silicon designs for RISC-V compute platforms
Domain
Semiconductor / Chip Design / RISC-V
Required skills
SystemVerilog, UVM, digital logic design, computer architecture, functional coverage, debugging tools (Verdi/DVE), on-chip protocols (AXI, PCIe, etc.), scripting (Python/Perl/Tcl)
Preferred skills
Mentorship, cross-functional collaboration
Technologies
SystemVerilog, UVM, Verdi, DVE, Python, Perl, Tcl, AXI, AHB, APB, PCIe, NVMe, USB, Ethernet
Responsibilities
Define and author comprehensive verification plans; Design and maintain scalable constrained-random verification environments; Define verification strategies incorporating simulation and formal techniques; Debug complex test failures and identify RTL/testbench defects; Analyze functional and code coverage to drive closure; Mentor junior verification engineers
Seniority
Senior, hands-on IC
