Senior / Staff Design Verification Engineer
Core
Ensuring functional correctness of complex, next-generation SoCs/IPs through the entire verification lifecycle.
Role type
Senior Design Verification Engineer (ASIC/SoC)
Builds
Tape-out-ready silicon designs for RISC-V compute platforms
Domain
Semiconductor / Chip Design / RISC-V
Deliverable
production ML models | product features | dashboards & analysis | research | client delivery | infrastructure | physical/clinical work
Required skills
SystemVerilog, UVM, digital logic design, computer architecture, coverage closure, debugging RTL/TB bugs, on-chip protocols (AXI, PCIe, etc.), scripting (Python/Perl/Tcl)
Preferred skills
Mentorship of junior engineers, formal verification techniques
Technologies
Verdi, DVE, Python, Perl, Tcl, Shell
Responsibilities
Define and author comprehensive verification plans; Design and maintain scalable constrained-random verification environments; Define verification strategies at block/SoC levels; Debug complex test failures and root-cause RTL/TB bugs; Analyze and drive coverage closure to 100%; Provide technical guidance and mentorship to junior engineers
Seniority
Senior, hands-on IC
