Sr. ASIC Layout Design Engineer
Core
Senior Analog/Mixed-Signal Layout Design Engineer developing high-performance focal-plane array readout integrated circuits (ROICs) for infrared detectors, sensors, and cameras.
Role type
Senior IC layout design engineer
Builds
High-performance analog/mixed-signal ICs (ROICs) for infrared imaging systems
Domain
Semiconductor / Analog & Mixed-Signal IC Design
Required skills
Analog/mixed-signal layout design, CMOS circuit layout, Cadence Virtuoso XL, Calibre verification (DRC/LVS), floor-planning, placement, routing, PDK usage, SKILL/TCL/Python scripting
Preferred skills
Focal-plane array experience, 180nm/130nm/75nm process nodes, custom cell-based layout
Technologies
Cadence Virtuoso XL, Calibre, SKILL, TCL, Shell, Python
Responsibilities
Develop analog/mixed-signal IC layouts and create GDS databases; Optimize floor-planning, placement, and routing with circuit designers; Ensure layout integrity via DRC, LVS, and PEX; Interface with ROIC, detector, and systems teams; Present project updates and prepare design review reports; Handle export-controlled information per GTC protocol; Maintain design documents per ISO quality system requirements
Seniority
Senior, hands-on IC
