Sr. ASIC Layout Design Engineer
Core
Develop high-performance focal-plane array readout integrated circuits (ROICs) for infrared detectors, sensors, and cameras used in aerospace, defense, and scientific research.
Role type
Senior IC layout design engineer (analog/mixed-signal)
Builds
High-performance ROICs for infrared imaging systems
Domain
Semiconductor design, analog/mixed-signal ICs, infrared sensors
Deliverable
production ML models | product features
Required skills
Analog/mixed-signal layout design, CMOS circuit layout, floor-planning, placement, routing, DRC/LVS/PEX verification, PDK usage, GDS database creation, SKILL/TCL/Python scripting
Preferred skills
Focal-plane array experience, 180nm/130nm/75nm process node expertise, wire resistance/coupling capacitance knowledge
Technologies
Cadence Virtuoso XL, Calibre, Siemens tools
Responsibilities
Develop analog/mixed-signal IC layouts and create GDS databases; Optimize floor-planning, placement, and routing with circuit designers; Ensure layout integrity and compliance with foundry fabrication rules; Interface with detector, systems, and packaging teams; Prepare design review reports and present to customers; Handle export-controlled information and follow GTC protocols; Maintain design documents per ISO quality system requirements
Seniority
Senior, hands-on IC
