Verification Engineer
Core
Verify blocks and subsystems of a first-of-its-kind chiplet using UVM testbenches, driving coverage to closure, and debugging across simulation and emulation.
Role type
Senior IC ASIC/SoC functional verification engineer
Builds
Chiplet verification infrastructure, UVM testbenches, and coverage models for optical interconnects
Domain
Semiconductor hardware design, optical interconnects, chiplet architecture
Deliverable
production ML models | product features | dashboards & analysis | research | client delivery | infrastructure | physical/clinical work
Required skills
UVM/SystemVerilog, constrained-random verification, functional coverage closure, simulation debugging, Python/Perl/TCL scripting, regression flow management
Preferred skills
High-speed SerDes/PAM4/FEC verification, UCIe/PCIe/CXL VIP, mixed-signal verification, hardware-assisted verification (emulation/FPGA), low-power/UPF verification, formal verification
Technologies
UVM, SystemVerilog, UCIe, Palladium, Veloce, HAPS, Protium, UPF
Responsibilities
Build and extend UVM testbenches (agents, sequences, scoreboards); write directed and constrained-random tests; verify engines against golden models with error injection; integrate VIPs for compliance and link-training scenarios; run regressions and triage failures; register verification and firmware co-simulation; support hardware-assisted verification on emulation/FPGA; participate in gate-level and low-power verification
Seniority
Senior, hands-on IC
