Custom Layout Designer (Analog Layout Designer)
Core
Designing high-speed, high-accuracy CMOS integrated circuits IP blocks (analog/mixed-signal) for consumer, industrial, and automotive markets using leading-edge silicon processes.
Role type
Senior IC analog layout engineer
Builds
High-quality IP blocks, test-chips, and custom layout designs for foundry processes down to 5nm and below
Domain
Semiconductor / Analog IC Design
Required skills
Analog layout techniques (matching, shielding), floor planning, physical verification, foundry design rule conformance, circuit layout effects (speed, capacitance, power, area), Cadence Virtuoso tools, FinFET/GAA layout knowledge
Preferred skills
Microelectronics design exposure, R&D collaboration experience
Technologies
Cadence Virtuoso, PVS, Cadence layout and verification tools
Responsibilities
Implement high-speed/high-accuracy cells and IP blocks, collaborate with global circuit designers on technical needs, work with R&D teams to develop layout editing and verification tools, perform back-end flow from floor planning to final verification
Seniority
Senior, hands-on IC
