Lead Design Engineer
Core
Lead verification strategy, architecture, and execution for semiconductor/ASIC/SoC designs using UVM/SystemVerilog.
Role type
Senior IC Digital Verification Engineer (DV)
Builds
Verification environments, testbenches, and sign-off deliverables for chip designs
Domain
Semiconductor / ASIC / SoC / Digital Verification
Required skills
UVM, SystemVerilog, Constraint Random Testing, Formal Verification, Debugging, Coverage Analysis, Gate-Level Simulation, Testbench Architecture, Root-cause Analysis
Preferred skills
Mentorship, Cross-functional Collaboration, Project Management
Technologies
UVM, SystemVerilog, Formal Tools, GLS
Responsibilities
Define verification strategy and methodology; Design scalable verification environments including BFMs and monitors; Write complex test cases and sequences; Lead root-cause analysis of design bugs; Implement constrained-random stimulus generation; Oversee gate-level simulation and provide final technical approval.
Seniority
Senior, hands-on IC
