Design Engineer II
Core
Frontend Design Engineer for Advanced Physical IP Development, focusing on high-performance Consumer PHYs (eUSB2v2, USB4-PHY, PCIe, ONFI, eDP/DP, SATA) and digital RTL implementation.
Role type
Design Engineer II (Frontend ASIC/PHY)
Builds
Physical IP for industry-standard protocols for global customers in consumer, hyperscale, automotive, and aerospace sectors.
Domain
Electronic Design Automation (EDA), Semiconductor, ASIC Design
Deliverable
production ML models
Required skills
RTL design, ASIC end-to-end methodology, low-power design, digital verification collaboration, serial interface standards (USB, PCIe, DP, Ethernet), synthesis and constraint generation, DFT, power management
Preferred skills
High-speed serial interface link IPs in advanced nodes, System Verilog, Python, C/C++, Cadence ASIC design tools, Analog Mixed-Signal basics, SI/PI, Post-Silicon Validation
Technologies
Verilog, System Verilog, Python, C/C++, Cadence ASIC tools, FPGA, Palladium
Responsibilities
RTL implementation and feature refinement, specification definition, low-power design features (power islands, state retention), defining verification coverage and testing strategies, collaborating with analog/layout/backend teams, pre/post-silicon application support
Seniority
Mid-level IC (1+ years experience)
