Design Engineer
Core
Custom Layout Design Engineer responsible for floorplanning, resistor/capacitor placement, routing, and noise reduction for high-speed mixed-signal PHYs.
Role type
Senior IC analog layout engineer
Builds
Custom layout floorplans and routing for SerDes, USB, DDR, and other high-speed mixed-signal interfaces
Domain
Semiconductor IC design, analog/mixed-signal
Required skills
Analog/custom layout design, DRC/LVS/ERC analysis, EMIR analysis, Virtuoso XL, Pegasus/Calibre DRC/LVS, Voltus-FI, high-speed mixed-signal PHY design, IC design technology and process methodology
Preferred skills
PERC run experience, FinFET layout experience, ESD/Latch-up experience, digital P&R team cooperation
Technologies
Virtuoso XL, Pegasus, Calibre, Voltus-FI
Responsibilities
Create custom layout floorplans and top-level hierarchies; place resistors and capacitors; route sensitive and mixed-signal signals; perform DRC/LVS/ERC and EMIR analysis; collaborate with analog circuit design teams
Seniority
Mid-level, hands-on IC
