Design Engineer
Core
Custom layout floorplan, matching guides, resistor/capacitor placement, noise reduction, and routing for high-speed mixed-signal PHYs.
Role type
Senior IC analog/custom layout engineer
Builds
Custom layout top-level hierarchy floorplans for blocks/powers and high-speed mixed-signal PHYs (SerDes, USB, DDR)
Domain
Semiconductor IC design, analog/mixed-signal
Deliverable
production ML models | product features | dashboards & analysis | research | client delivery | infrastructure | physical/clinical work
Required skills
Analog/custom layout design, DRC/LVS/ERC analysis, EMIR analysis, Virtuoso XL, Pegasus/Calibre DRC/LVS, Voltus-FI, IC design technology and process methodology
Preferred skills
PERC run experience, FinFET layout experience, ESD/Latch-up experience, digital P&R team cooperation
Technologies
Virtuoso XL, Pegasus, Calibre, Voltus-FI
Responsibilities
Create custom layout floorplans and matching guides; place resistors and capacitors; route sensitive and mixed-signal signals; collaborate with analog circuit design teams; perform DRC/LVS/ERC and EMIR analysis
Seniority
Mid-level, hands-on IC
