Staff Analog Design Engineer, SerDes Clocking
Core
Hands-on transistor-level analog design of the clocking subsystem (PLL, DLL, phase interpolator, CDR) for high-speed SerDes IO chiplets to ensure link closure and timing/jitter budget compliance.
Role type
Staff Analog Design Engineer (SerDes Clocking)
Builds
High-speed SerDes clocking blocks and IO chiplets for generative AI infrastructure
Domain
Semiconductor hardware design, Analog/Mixed-Signal, High-Speed SerDes
Deliverable
production ML models | product features
Required skills
Transistor-level analog design, PLL/DLL/CDR architecture, Phase noise analysis, Jitter budgeting, Deep sub-micron circuit design (FinFET/GAA), Layout design (inductors/VCOs), Silicon bring-up and characterization, Simulation (Cadence Virtuoso, Spectre, MATLAB/Python)
Preferred skills
Die-to-die interconnect (UCIe, BoW), Forwarded-clock architectures, Digital/hybrid PLL/CDR calibration, Knowledge of UCIe/OIF/IEEE/PCIe specs, Cross-node porting experience
Technologies
Cadence Virtuoso, Spectre, MATLAB, Python, Verilog-A, BERTs, Phase noise analyzers, High-speed oscilloscopes
Responsibilities
Design low-jitter frequency synthesis (PLL/VCO/loop filter), Design phase interpolators and rotation schemes, Design high-frequency clock distribution (buffers, skew control), Define and verify CDR architecture and loop dynamics, Build phase-noise/jitter budgets, Create verification environments (PSS/HB/Monte Carlo), Drive layout and silicon bring-up/characterization
Seniority
Staff, hands-on IC