Sr Principal Design Engineer
Core
Senior Principal Digital Implementation Engineer providing technical leadership for complex silicon development programs from synthesis to tapeout.
Role type
Senior Principal IC Design Engineer (Digital Implementation)
Builds
Advanced-node digital chips (CPUs, GPUs, AI/ML accelerators, networking SoCs)
Domain
Semiconductor / Electronic Design Automation (EDA)
Deliverable
production ML models | product features
Required skills
Advanced-node digital implementation, RTL-to-GDSII flows, Physical design and optimisation, Timing closure and signoff, Power optimisation and analysis, Signal integrity, SoC integration, IP integration, DTCO, Advanced packaging, Methodology development
Preferred skills
AI acceleration, Technical team leadership, Customer strategy influence
Technologies
EDA tools, Advanced process nodes, SoC design flows
Responsibilities
Provide technical leadership for complex silicon programs from synthesis to tapeout, Develop advanced methodologies for PPA objectives, Collaborate with R&D to drive tool enhancements, Lead technical investigations into silicon failures and convergence challenges, Mentor implementation engineers, Represent Cadence as a technical thought leader with strategic customers
Seniority
Principal, hands-on technical leadership with mentorship