Principal Signoff CAD Engineer
Core
Architect and own the end-to-end silicon signoff CAD flow strategy for advanced-node silicon programs, ensuring production-quality convergence for timing, power, and physical verification.
Role type
Principal Signoff CAD Engineer (Silicon Signoff)
Builds
Production-quality silicon signoff flows and validation frameworks for advanced-node chips
Domain
Semiconductor / EDA / Silicon Signoff
Deliverable
production ML models | product features | dashboards & analysis | research | client delivery | infrastructure | physical/clinical work
Required skills
Parasitic extraction (StarRC/Pegasus), Static timing analysis (PrimeTime/Tempus), Power integrity and IR-drop analysis (Redhawk-SC/Voltus), Physical verification, Advanced process node expertise (5nm and below), Scripting and automation (TCL/Python), Tool ecosystem evaluation (Synopsys/Cadence), Team leadership, Flow architecture design
Preferred skills
Cloud-based EDA compute environments, Modern CI/CD practices for CAD flow development
Technologies
StarRC, Pegasus, PrimeTime, Tempus, Redhawk-SC, Voltus, Fusion Compiler, Innovus, TCL, Python
Responsibilities
Establish best practices and quality metrics for signoff methodologies, Collaborate with physical design and front-end RTL teams for seamless integration, Drive deep quality improvements to prevent silicon escapes, Grow the signoff engineering team and establish technical standards, Serve as the technical authority for signoff decisions and trade-offs, Lead signoff convergence on multiple concurrent tapeouts
Seniority
Principal, strategy & mentorship
