Principal Physical Design Engineer / Physical Design – ACE US
Core
End-to-end physical design execution for advanced semiconductor SoCs from RTL to silicon, optimizing Power, Performance, and Area (PPA) at technology nodes like 5nm.
Role type
Principal Physical Design Engineer (SoC Implementation)
Builds
Flagship System-on-Chip (SoC) products for advanced semiconductor applications
Domain
Semiconductor / ASIC Physical Design
Required skills
Floorplanning, Synthesis, Place & Route, CTS, Routing, Static Timing Analysis (STA), Physical Design Verification (DRC/LVS/ERC), Low Power Design (UPF/CLP), Scripting (Python, TCL, Perl), EDA Tool expertise (Synopsys, Cadence)
Preferred skills
High-reliability SoC experience, AI-driven design methodologies, Automation flow optimization
Technologies
Cadence, Synopsys, Python, TCL, Perl, 5nm, 16nm
Responsibilities
Lead full RTL-to-GDSII implementation flow including signoff; Drive timing, power, and physical verification closure; Define and deploy next-generation physical design methodologies; Collaborate with architecture, RTL, and verification teams; Mentor team members and drive automation.
Seniority
Principal, hands-on IC with leadership
