Principal Design Engineer
Core
Lead major blocks of Memory PHY layout design and perform hands-on design of critical analog and high-speed layout blocks for FinFET technology.
Role type
Principal Design Engineer (Memory PHY Layout)
Builds
Memory PHY layout blocks for semiconductor chips
Domain
Semiconductor / Analog Mixed-Signal / Custom Layout
Deliverable
production ML models | product features | dashboards & analysis | research | client delivery | infrastructure | physical/clinical work
Required skills
FinFET technology layouts, 3nm/5nm/7nm technology nodes, custom layout design, high-speed analog mixed-signal layout
Preferred skills
high-speed analog mixed-signal layout
Technologies
FinFET, 3nm, 5nm, 7nm
Responsibilities
Own and lead major blocks of Memory PHY Layout design, Perform hands-on design of critical analog and high-speed layout blocks, Coordinate design work with Circuit leads, layout contractors and layout team members, Participate in layout reviews by presenting and reviewing custom layout designs
Seniority
Principal, hands-on IC