DDR Design Verification Staff Engineer
Core
Design verification engineer for LPDDR/DDR based IPs and Subsystems in the Infra IP team.
Role type
Staff Digital Design Verification Engineer
Builds
Verification infrastructure, VIPs, test plans, and coverage for memory subsystems
Domain
Semiconductor / Hardware Engineering / Memory Interfaces
Required skills
System Verilog, UVM, Debug, Test Plan Development, Assertions, Coverage Analysis, Bus Protocols (AHB/AXI/ACE)
Preferred skills
DDR/LPDDR families (DDR2/3/4/5), Digital design concepts, DV methodologies and tools, Scripting
Technologies
System Verilog, UVM, AHB, AXI, ACE, ACE-Lite, DDR, LPDDR
Responsibilities
Create DV infrastructure for verification, Integrate VIPs, Create and execute test plans, Debug failures and write assertions, Ensure high quality verification
Seniority
Staff, hands-on IC
