Layout Designer Intern
Citizens or permanent residents only
Core
Internship role translating transistor-level circuit designs into physical integrated circuit layouts for analogue and mixed-signal ICs.
Role type
IC Layout Engineer Intern
Builds
Physical layouts for analogue and mixed-signal integrated circuits
Domain
Semiconductor / IC Design
Required skills
IC layout methods, semiconductor device physics, DRC, LVS, Cadence Virtuoso
Preferred skills
Knowledge of fabrication processes, physical verification debugging
Technologies
Cadence Virtuoso
Responsibilities
Learn IC layout methods, translate block-level circuit designs into physical layouts, perform physical verification (DRC/LVS), document work and present findings
Seniority
Intern
