Staff Engineer, Design Verification Engineering
Core
Architect and lead verification strategies for complex analog and mixed-signal semiconductor designs, ensuring product quality and reliability.
Role type
Staff Design Verification Engineer (Mixed-Signal/Analog)
Builds
Verification environments and test strategies for analog/mixed-signal chips
Domain
Semiconductor / Analog & Mixed-Signal Design
Required skills
SystemVerilog, UVM, Mixed-Signal Verification, Debugging (RTL/Gate-level), EDA Tools (Cadence/Synopsys), Python/Perl/TCL/Shell scripting
Preferred skills
MS/PhD in EE/CE, 7-10+ years in digital design verification
Technologies
SystemVerilog, UVM, Cadence, Synopsys, Python, Perl, TCL, Shell
Responsibilities
Architect verification strategy for complex designs, Design and implement UVM-based environments, Mentor junior engineers, Coordinate with design teams, Lead complex debugging efforts, Drive coverage closure, Lead post-silicon validation, Serve as principal customer contact
Seniority
Staff, technical leadership & mentorship
