Senior Digital Verification Engineer
Core
Architect and develop robust verification environments for complex digital IPs, planning full lifecycle verification from planning to coverage closure.
Role type
Senior IC digital verification engineer (VLSI)
Builds
Verification environments for next-generation memory products (SSD, eMMC/UFS)
Domain
Semiconductor / Memory / VLSI
Required skills
SystemVerilog, UVM, Python scripting, VLSI verification methodology, test planning and execution, debug and coverage closure
Preferred skills
Linux/Unix environments, Cadence tools (Xcelium, vManager, Indago) (via careerplan.io/jobs/D4-005-E2-374-senior-digital-verification-engineer-at-samsung-research-and-development-center-israel)
Technologies
SystemVerilog, UVM, Python, Xcelium, vManager, Indago
Responsibilities
Plan verification of complex digital IPs, architect and develop verification environments from scratch, debug tests with design engineers, execute tests and achieve coverage closure
Seniority
Senior, hands-on IC
