Junior Digital Verification Engineer
Core
Junior Digital Verification Engineer supporting the full verification cycle for complex digital designs in Samsung's Flash memory division.
Role type
Junior IC digital verification engineer
Builds
SSD, eMMC/UFS, and emerging memory products
Domain
Semiconductor hardware verification
Required skills
SystemVerilog, UVM, SystemVerilog Assertions (SVA), test execution, coverage analysis, debugging, trace analysis, regression testing
Preferred skills
Python scripting, Linux/Unix environments, Cadence Xcelium, vManager, Indago
Responsibilities
Join the full verification cycle for complex digital designs from planning to coverage closure; Implement SystemVerilog Assertions (SVA) and drive deep code coverage analysis; Debug complex tests and trace analysis alongside design engineers; Collaborate closely with design and algorithm engineers (via careerplan.io/jobs/D4-005-E2-372-junior-digital-verification-engineer-at-samsung-research-and-development-center-israel)
Seniority
Junior, hands-on IC
