Senior Digital Verification Engineer (CIS)
Core
Senior Digital Verification Engineer responsible for the full life cycle of verification from planning to test execution and coverage closure for complex digital designs.
Role type
Senior IC digital verification engineer
Builds
Verification environments and functionally correct digital blocks/systems
Domain
Semiconductor / Digital IC Design
Required skills
System Verilog, UVM, Perl, Python, verification methodologies, test execution, coverage closure, design specification analysis, debugging
Technologies
System Verilog, UVM, Perl, Python
Responsibilities
Plan verification of complex digital designs from block to system level; Execute verification tests and achieve coverage closure; Debug tests with design engineers to deliver functionally correct blocks; Collaborate with Design, Algorithm, FW, and Analog engineers (via careerplan.io/jobs/D4-005-52-36A-senior-digital-verification-engineer-cis-at-samsung-research-and-development-center-israel)
Seniority
Senior, hands-on IC
