Sr Physical Design Engineer
Core
Own and drive full-chip and block-level physical verification (PV) signoff activities, including DRC, LVS, PEX, and EM/IR drop analysis for analog, digital, and mixed-signal designs.
Role type
Senior IC physical design engineer (physical verification)
Builds
Semiconductor chips (analog, digital, mixed-signal) for the Intelligent Edge
Domain
Semiconductor / Physical Design / Physical Verification
Required skills
Physical verification methodologies, DRC/LVS/PEX/PERC/ERC/Antenna checks, Electromigration (EM) and IR Drop analysis, Python/Tcl/Shell/SKILL scripting, Power grid optimization, Tapeout readiness review
Preferred skills
Mentorship, automation development, continuous improvement in PV/EMIR methodology
Technologies
Python, Tcl, Shell, SKILL, EDA tools
Responsibilities
Perform and debug DRC, LVS, PEX, PERC/ERC, and Antenna verification; Analyze and resolve complex PV violations; Develop automation scripts and dashboards for signoff metrics; Collaborate with layout, circuit, and CAD teams for power delivery optimization; Mentor junior engineers
Seniority
Senior, hands-on IC
