Senior Engineer -Low Power CLP
Core
Senior engineer responsible for low-power structural verification and logical equivalence checking (LEC) to ensure quality silicon tapeout for complex SoC and IP designs.
Role type
Senior IC verification engineer (low-power & LEC)
Builds
High-quality silicon tapeouts for System-on-Chips (SoCs) and Intellectual Property (IP)
Domain
Semiconductor / Hardware Design / Low-Power Verification
Required skills
UPF/CPF, SystemVerilog, Cadence Conformal Low Power (CLP), Synopsys VCLP, Logic Equivalence Checking (LEC), TCL, Perl, Python, RTL-to-Gate verification, Power-aware equivalence checking
Preferred skills
Synthesis flows, Place & Route (P&R) flows
Technologies
Cadence Conformal LEC, Cadence Conformal Low Power (CLP), Synopsys VCLP, UPF, CPF, SystemVerilog, TCL, Perl, Python (via careerplan.io/jobs/101307117584-senior-engineer-low-power-clp-at-arm)
Responsibilities
Perform low-power verification using CLP or VCLP; Verify and validate UPF implementation across RTL, netlist, and physical design stages; Perform power-aware equivalence checking and resolve issues; Analyze, debug, and resolve CLP structural and power-aware verification failures; Perform RTL-to-Synthesis, Synthesis-to-P&R, and ECO logic equivalence verification using LEC; Develop, automate, and maintain robust LEC flows and signoff methodologies; Develop TCL, Perl, and Python scripts to automate verification tasks.
Seniority
Senior, hands-on IC
