Principal Design Engineer
Core
Designing and integrating RTL subsystems and SoC logic for IoT, Automotive, Client, and Infrastructure computing systems.
Role type
Principal Design Engineer (SoC/RTL)
Builds
Sophisticated processing systems and subsystems for IoT, Automotive, Client, and Infrastructure computing
Domain
Semiconductor / SoC Design
Required skills
Verilog HDL, SystemVerilog, SoC development, static design checks (CDC, RDC, X-prop, Lint, UPF), synthesis, timing analysis, power management, microarchitecture specification
Preferred skills
ARM-based designs, AMBA protocols (ACE-Lite, AXI, AHB, APB, CHI), processor subsystems, Interconnects, security subsystems, PCIe subsystems, Perl, Python
Technologies
Verilog, SystemVerilog, Perl, Python, AMBA, ARM
Responsibilities
Develop subsystem microarchitecture specifications and RTL, review verification test plans, debug and fix design issues, evaluate system KPIs with performance/power teams, propose IP refinements, enhance design methodologies, manage project plans and schedules
Seniority
Senior, hands-on IC
