Principal Engineer, Design Verification Engineering
Core
Architecting and executing pre- and post-silicon verification for digital designs, sub-systems, and SoCs using System Verilog and UVM.
Role type
Principal Engineer, Design Verification
Builds
Verification environments, testbenches, and test infrastructure for chip-level and block-level verification
Domain
Semiconductor / Digital Design Verification
Deliverable
production ML models | product features | dashboards & analysis | research | client delivery | infrastructure | physical/clinical work
Required skills
System Verilog, UVM, OVM, Verilog, C++, C++, transaction level modeling, constrained random techniques, assertion-based verification, coverage analysis, Python, Perl, Shell scripting, Perforce, Git, EDA tools, ARM architecture, RISC-V architecture
Technologies
System Verilog, UVM, OVM, Verilog, C++, Python, Perl, Shell, Perforce, Git, EDA tools
Responsibilities
Architect testbenches and develop test infrastructure; Integrate block-level testbenches into chip-level UVM environments; Define test plans and verification methodologies; Collaborate with design teams for code and functional coverage closure; Support post-silicon verification activities
Seniority
Principal, hands-on IC
