Verification Engineer
Core
Develop and architect verification environments for FPGA, signal processing, and controller projects using UVM methodology.
Role type
Senior IC verification engineer (FPGA/ASIC)
Builds
Verification environments for FPGA/ASIC designs
Domain
Semiconductor hardware verification (via careerplan.io/jobs/15-007-B2-27E-verification-engineer-at-abra)
Required skills
UVM methodology, SystemVerilog, RTL debugging, Python scripting, TCL scripting, Bash scripting, Linux environment usage, FPGA development collaboration
Preferred skills
Questa Simulator, Electrical/Electronics/CS degree
Technologies
UVM, SystemVerilog, Questa Simulator, Python, TCL, Bash, Linux
Responsibilities
Develop verification environments using UVM methodology for FPGA verification; Define, architect, and develop verification environments from block-level to full-chip level; Support RTL debugging from block level to system level; Work closely with FPGA development, system, architecture, and algorithm teams.
Seniority
Mid-level, hands-on IC
