Mixed Signal Verification Engineer
Core
Architecting and owning mixed-signal verification environments for audio solutions in portable, wearable, and gaming markets.
Role type
Principal Mixed Signal Design Verification Engineer
Builds
Production audio SoCs and mixed-signal sub-systems for consumer electronics
Domain
Semiconductor / Analog & Mixed Signal / Audio
Deliverable
production ML models | product features
Required skills
UVM-based testbench architecture, SystemVerilog Real-Number Modeling, functional coverage closure, behavioral modeling of analog blocks, DMS netlist generation, Gate Level Simulation (GLS), scripting (Python/Perl/Makefile), assertion development
Preferred skills
AHB/AXI/APB protocols, Audio Interface knowledge, Power aware simulations, Formal Verification, Audio IP verification, DSP concepts
Technologies
UVM, SystemVerilog, Cadence Virtuoso, Python, Perl, Makefile
Responsibilities
Define test plans and methodologies for chip-level verification, mentor less-experienced verification engineers, support post-silicon verification activities, improve DV methodologies and automation, interact with analog mixed signal and firmware teams
Seniority
Principal, hands-on IC with people management potential