Staff Engineer, Static Timing Analysis CAD Engineer
Core
Ensuring timing integrity and signoff readiness for next-generation GPU IPs used in premium smartphones and high-performance computing devices.
Role type
Staff Static Timing Analysis (STA) CAD Engineer
Builds
Automation and methodologies for timing analysis to ensure convergent strategies for complex advanced node designs.
Domain
Semiconductor / ASIC Design / GPU IP
Deliverable
production ML models | product features | dashboards & analysis | research | client delivery | infrastructure | physical/clinical work
Required skills
STA methodologies (LLE, POCV, derating), ASIC design flows, clock tree synthesis (CTS), multi-voltage/multi-clock design, formal equivalency checks, low-power checks (UPF), scripting (Tcl, Python, Perl, Shell), industry-standard STA tools (PrimeTime, StarRC, PrimeClosure, Tempus)
Preferred skills
AI application for engineering tasks, multi-corner analysis, low-power constraints
Technologies
PrimeTime, StarRC, PrimeClosure, Tempus, Tcl, Python, Perl, Shell
Responsibilities
Develop and implement automation for timing analysis; test and debug unexpected issues with new technology node bring up; contribute to technical excellence by applying and influencing STA methodologies and sign-off flows; take initiatives on moderate-to-complex projects; utilize AI to improve daily engineering efficiency.
Seniority
Staff, hands-on IC
