Physical Verification and EMIR Signoff Lead
Core
Lead Physical Verification (PV) and Electromigration/IR Drop (EMIR) sign-off activities for advanced semiconductor chips.
Role type
Senior IC Physical Verification and EMIR Signoff Lead
Builds
Tapeout-ready chip designs for Samsung's System LSI, Memory, and Foundry solutions
Domain
Semiconductor / VLSI Design
Deliverable
production ML models | product features | dashboards & analysis | research | client delivery | infrastructure | physical/clinical work
Required skills
Physical Design Verification, EMIR methodology, DRC, LVS, ERC, DFM, ESD, Antenna, PERC, Static/Dynamic IR, Signal/Power EM, ESR, Jitter checks, Calibre, ICV, Redhawk, Voltus, Innovus, FC tools, low technology nodes (8nm/5nm/3nm/2nm), automated verification flow, Unix, Perl, Python, TCL
Preferred skills
Technical leadership, process and methodology improvements
Technologies
Calibre, ICV, Redhawk, Voltus, Innovus, FC
Responsibilities
Own and execute PV and EMIR activities including DRC, LVS, ERC, DFM, ESD, Antenna, PERC, Static IR, Dynamic IR, Signal/Power EM, ESR and Jitter checks; Develop and manage automated verification flow and scripts in Unix, Perl, Python, and TCL; Collaborate with PD, Design/DfT, Foundry, Package, and Technology experts on PV and EMIR issues; Provide technical leadership to juniors and drive process improvements
Seniority
Senior, hands-on IC