Engineer/Staff Engineer – Multi-Dies Physical Verification Engineer
Core
Define and enable physical sign-off flows and solutions for SoC and Multi-Dies (3D IC) design to ensure first-time success in product tape-out.
Role type
Staff Engineer, Multi-Dies Physical Verification
Builds
Physical verification sign-off flows and solutions for 3D IC tape-out
Domain
Semiconductor / 3D IC / Advanced Process Nodes
Deliverable
production ML models | product features | dashboards & analysis | research | client delivery | infrastructure | physical/clinical work
Required skills
Multi-Dies Physical Verification, 3D_Stack, 3D_PERC, 3D_ANT, DRC, LVS, ANT, ERC, ESD, automation solutions, tape-out flow coordination
Responsibilities
Responsible for Multi-Dies Physical Verification Sign-off in area of (3D_Stack, 3D_PERC, 3D_ANT) for tape-out; Co-work with Package Design Team to resolve Multi-Dies integration issues; Co-work with ESD Team to run 3D_PERC flow; Coordinates with Chip PV Team on active dies related issues (DRC, LVS, ANT, ERC, ESD); Provide automation solutions to improve efficiency in tape-out flow; Report on Tapeout PV issues.
Seniority
Staff Engineer, hands-on IC
