Full-Chip Physical Design Verification Engineer
Core
Drive full-chip signoff and ensure manufacturable, high-quality silicon across advanced technology nodes by leading physical verification closure.
Role type
Senior IC SoC Physical Design Verification Engineer
Builds
High-performance RISC-V CPU and AI platform SoCs
Domain
Semiconductor / Advanced Node SoC Design
Deliverable
production ML models
Required skills
DRC, LVS, ERC, PERC, Antenna, DFM verification; ESD planning; padring integration; bump/RDL strategies; reliability analysis (IR drop, EM); advanced node design (7nm, 5nm, 3nm); Python/TCL scripting
Preferred skills
Mentorship; cross-functional collaboration
Technologies
Calibre, ICV, Pegasus, FC, Innovus
Responsibilities
Lead physical verification closure (DRC, LVS, ERC, etc.); debug issues using standard industry PV tools; collaborate across RTL, PD, CAD, and packaging teams to achieve successful tapeouts
Seniority
Senior, hands-on IC