Senior Principal Engineer
Core
Architecting and delivering breakthrough FPGA physical synthesis, timing optimization, and implementation methodologies to improve quality of results, runtime, and scalability for large-scale designs.
Role type
Senior Principal Engineer (EDA/FPGA optimization)
Builds
Next-generation FPGA compiler technologies and production tool flows
Domain
Semiconductor design automation (EDA) / FPGA physical design
Required skills
EDA algorithms, optimization engines, design compilation, C++, data structures, performance optimization, physical synthesis, timing analysis, placement and routing, static timing analysis, large-scale software architecture
Preferred skills
Path-based optimization, timing-driven synthesis, machine learning for EDA, patent portfolio, technical publications, Distinguished Engineer experience
Technologies
C++, FPGA tools, ASIC implementation tools
Responsibilities
Define architectural roadmap for FPGA compiler technologies, design advanced optimization algorithms for timing closure and area reduction, lead development of timing-driven optimization methodologies, architect scalable solutions for hierarchical designs, partner with cross-functional teams to integrate technologies, analyze customer workloads and benchmark results, mentor engineers on architectural initiatives
Seniority
Principal, hands-on IC with strategic influence