Senior Physical Design Engineer
Core
Implement custom IP and SoC designs from RTL through GDSII, driving physical implementation, timing closure, power optimization, and design signoff for next-generation FPGA products.
Role type
Senior IC physical design engineer (FPGA/ASIC)
Builds
Manufacturing-ready design databases for FPGA products
Domain
Semiconductor / FPGA / Digital ASIC
Deliverable
production ML models | product features | dashboards & analysis | research | client delivery | infrastructure | physical/clinical work
Required skills
RTL-to-GDSII physical design flow, synthesis, floorplanning, place and route, clock tree synthesis (CTS), static timing analysis (STA), timing closure, physical verification, DRC, LVS, ERC, signoff methodologies, PPA optimization, multi-voltage/power domain analysis
Preferred skills
Advanced semiconductor process nodes (7nm, 5nm, 3nm), DFT-aware physical design flows, physical design automation scripting (Python, Tcl, Perl, Shell), large-scale SoC or FPGA architectures, power integrity, IR drop, electromigration (EM), signal integrity analysis
Technologies
Synopsys Fusion Compiler, ICC2, PrimeTime, Cadence Innovus
Responsibilities
Execute physical design flow including synthesis, floorplanning, place and route, CTS, STA, and power/clock distribution; Perform physical verification and signoff including formal equivalence checking, layout verification, and electrical rule checking; Analyze implementation results to identify violations and develop solutions; Optimize designs for power, performance, frequency, and area (PPA); Collaborate with cross-functional teams to resolve implementation challenges; Participate in developing and improving physical design methodologies and automation.
Seniority
Senior, hands-on IC
