Physical Design Engineer
Core
Physical implementation of next-generation FPGA products, optimizing designs for timing, power, area, and manufacturability.
Role type
Physical Design Engineer (Backend Implementation)
Builds
High-quality silicon for FPGA and ASIC-style designs
Domain
Semiconductor / FPGA / VLSI
Deliverable
production ML models | product features | dashboards & analysis | research | client delivery | infrastructure | physical/clinical work
Required skills
floorplanning, placement, clock tree synthesis (CTS), routing, static timing analysis (STA), timing closure, physical verification (DRC/LVS), design rule checks, scripting (Tcl/Python/Perl), digital design fundamentals, CMOS/VLSI concepts
Preferred skills
advanced-node physical design methodologies, low-power implementation, power planning, IR drop analysis, signal integrity, electromigration (EM) analysis, Linux/Unix development environments
Technologies
Cadence Innovus, Synopsys ICC2, PrimeTime, Fusion Compiler
Responsibilities
Support block-level and top-level physical design implementation including floorplanning, placement, CTS, routing, and physical verification; Optimize designs for timing, power, area, congestion, and routability; Run and analyze timing, power, congestion, and design rule reports to identify issues; Collaborate with RTL, DFT, CAD, and verification teams to resolve design and flow issues; Support static timing analysis, timing closure, and ECO implementation activities; Debug physical design issues related to setup/hold violations, clocking, congestion, IR drop, or design rule violations; Assist with physical verification tasks including DRC/LVS checks and design signoff preparation; Develop and maintain scripts and automation to improve physical design productivity and flow efficiency; Participate in silicon bring-up support and post-silicon debug activities
Seniority
Mid-level IC Engineer