FPGA Compiler (Placer) Engineer
Core
Develop and optimize FPGA placement algorithms within the compiler toolchain to improve timing, congestion, and resource utilization for complex designs.
Role type
Senior IC EDA algorithm engineer (FPGA placement)
Builds
FPGA compiler tools and placement algorithms
Domain
Semiconductor / EDA / FPGA physical design
Required skills
FPGA/ASIC CAD, EDA tools, algorithms and data structures, placement algorithms, C/C++, timing-driven optimization, congestion-driven optimization, ASIC/FPGA physical design methodologies, large-scale optimization
Preferred skills
FPGA toolchains (Quartus, Vivado), FPGA architectures, routing and timing closure, parallel/distributed algorithms, scripting (Python, Tcl)
Technologies
C/C++, Python, Tcl, Quartus, Vivado
Responsibilities
Design and implement FPGA placement algorithms; Contribute to end-to-end FPGA compilation flow; Improve runtime performance and scalability; Develop timing-aware placement strategies; Partner with architecture, routing, and STA teams; Analyze placement quality and timing bottlenecks; Integrate placement capabilities into compiler infrastructure
Seniority
Senior, hands-on IC