FPGA Compiler (Placer) Engineer
Core
Developing and optimizing FPGA placement algorithms within the compiler toolchain to improve timing, congestion, and resource utilization for complex designs.
Role type
Senior IC FPGA Compiler Engineer (Placer)
Builds
FPGA compiler toolchain components for AI, cloud, networking, and edge applications
Domain
Semiconductor / EDA / FPGA Physical Design
Deliverable
production ML models | product features
Required skills
FPGA/ASIC CAD, EDA tools, algorithms and data structures, placement algorithms, C/C++, analytical placement, simulated annealing, partitioning, clustering, timing-driven optimization, congestion-driven optimization, ASIC/FPGA physical design methodologies, large-scale optimization
Preferred skills
FPGA toolchains (Quartus, Vivado), FPGA architectures, routing and timing closure, parallel/distributed algorithms, scripting (Python, Tcl)
Technologies
Quartus, Vivado, C, C++, Python, Tcl
Responsibilities
Design and enhance placement algorithms; Contribute to end-to-end FPGA compilation flow; Improve runtime performance and QoR; Develop timing-aware placement strategies; Partner with architecture, routing, and STA teams; Analyze placement quality and drive convergence improvements; Integrate placement capabilities into compiler infrastructure
Seniority
Senior, hands-on IC
