High Level Synthesis Compiler Engineer
Core
Building reliable and scalable compiler tools that lower RTL and constraints into realizable FPGA designs, optimizing for quality-of-results and turnaround time.
Role type
Senior IC compiler engineer (EDA/FPGA flow)
Builds
Compiler infrastructure (IR, lowering, optimization passes) and integration with implementation/timing/debug flows
Domain
EDA, FPGA design, Compiler technology
Deliverable
production ML models | product features | infrastructure
Required skills
C++ (performance, multi-threading), LLVM/MLIR (IR design, passes, backends), digital design & FPGA primitives (LUT/FF/BRAM/DSP), timing analysis, synthesis/place-and-route flows
Preferred skills
PhD in EE/CS/CE, simulation/formal/debug environment experience, high-level design flows (HLS), shipping software to external customers
Technologies
C++, LLVM, MLIR, FPGA tools
Responsibilities
Develop and optimize compiler passes for IR lowering and QoR-driven optimizations; Work with customers to translate application goals into concrete flow improvements; Mentor engineers through code and design reviews; Document tool behavior, limitations, and workarounds
Seniority
Senior, hands-on IC with mentorship responsibilities
