ASIC Processor Complex Engineering Co-op (January 2027 - 4 months)
Core
Develop and evolve the processor complex for next-generation ASIC devices used in optical communications systems.
Role type
ASIC Design and Verification Co-op
Builds
Large-scale DSP ASICs for optical communications
Domain
Optical Communications / Semiconductor Design
Deliverable
production ML models | product features
Required skills
ASIC design, verification, System Verilog, UVM, Python scripting, firmware development, Linux development environments
Preferred skills
FPGA development, Agile methodologies, GIT
Technologies
System Verilog, UVM, Python, TCL, C, Java, Linux, JIRA, Confluence
Responsibilities
Develop small design blocks and analyze designs for correctness and speed; Implement and verify designs; Write verification testbenches (SV/UVM); Develop and enhance Python scripts for simulation regression and debug workflows; Code, build and test functions implemented in firmware.
Seniority
Student Co-op
