Design Verification Engineer (Silicon Engineering)
Core
Developing cutting-edge next-generation ASICs for deployment in space and ground infrastructures to enable global connectivity via the Starlink network.
Role type
Design Verification Engineer (Silicon Engineering)
Builds
Next-generation ASICs for Starlink satellites and ground infrastructure
Domain
Aerospace / Satellite Communications / ASIC Design
Deliverable
production ML models | product features | dashboards & analysis | research | client delivery | infrastructure | physical/clinical work
Required skills
SystemVerilog, UVM, Python, MATLAB, constrained random verification, test plan execution, functional coverage analysis, RTL design, chip bring-up, post-silicon validation
Preferred skills
Advanced degree in EE/CS, strong object-oriented programming, scripting languages
Technologies
SystemVerilog, UVM, Python, MATLAB
Responsibilities
Develop SystemVerilog testbench infrastructure (UVM and non-UVM) for testing designs including DSP blocks; Write and review test plans, develop test harnesses and test sequences; Execute test plans, run regressions, and achieve code and functional coverage closure; Automate test case generation using Python and MATLAB; Contribute to pre-silicon verification, chip bring-up, and post-silicon validation
Seniority
Entry-level to Mid-level, hands-on IC