Principal Design Verification Engineer (Silicon Engineering)
Core
Developing cutting-edge next-generation ASICs for deployment in space and ground infrastructures to enable global connectivity via the Starlink network.
Role type
Principal Design Verification Engineer (Silicon Engineering)
Builds
Next-generation ASICs for Starlink satellites and ground infrastructure
Domain
Aerospace / Satellite Communications / Silicon Design
Deliverable
production ML models | product features | dashboards & analysis | research | client delivery | infrastructure | physical/clinical work
Required skills
Digital ASIC and FPGA verification, UVM/OVM/VMM methodologies, Constrained random verification, Test bench development, Coverage modeling, Scripting (Python), RTL design, Chip bring-up, Post-silicon validation
Preferred skills
Advanced degree in EE/CE, Strong OOP knowledge, Problem-solving, Coding skills, Experience with complex digital designs
Technologies
UVM, OVM, VMM, Python, RTL, FPGA
Responsibilities
Lead and execute verification test plans from beginning to end, Contribute to pre-silicon verification, chip bring-up, and post-silicon validation, Execute steps to fully verify complex digital designs
Seniority
Principal, hands-on IC