ASIC Synthesis and STA Engineer - New Grad
Core
Execute frontend implementation for ASIC IP subsystems, focusing on synthesis, static timing analysis, logical equivalence checking, and clock domain crossing validation.
Role type
New Grad ASIC Synthesis and STA Engineer
Builds
Front-end implementation of ASIC IP subsystems for high-performance optical networking
Domain
Telecommunications / High-speed optical networking / ASIC design
Deliverable
production ML models | product features | dashboards & analysis | research | client delivery | infrastructure | physical/clinical work
Required skills
ASIC implementation flows, synthesis, static timing analysis, logical equivalence checking, clock domain crossing validation, RTL design principles, hardware description languages
Preferred skills
Floorplanning, Design for Testability (DFT), place and route, deepsubmicron ASIC technologies, advanced timing closure methodologies, scripting (Python, Tcl), DSP-centric development, EDA vendor collaboration
Technologies
Synthesis tools, Static Timing Analysis (STA) tools, EDA tools, Python, Tcl
Responsibilities
Execute frontend implementation for assigned IP subsystems, Develop and maintain timing constraints, Perform logical equivalence verification, Validate clock domain crossings, Create and optimize scripts and tools, Implement engineering change orders (ECOs)
Seniority
Entry-level (New Grad)