ASIC Design Engineer
Core
Define and architect high-performance blocks for next-generation networking ASICs, optimizing throughput and power efficiency.
Role type
Senior IC ASIC Design Engineer
Builds
Networking ASICs for protocols such as Ethernet and FCoE
Domain
Hardware engineering / Networking
Deliverable
production ML models | product features
Required skills
Verilog RTL coding, micro-architecture design, timing closure, multi-clock domain synchronization, high-speed serial interfaces, ASIC debugging
Preferred skills
Synopsys Design Compiler, Verplex LEC, SpyGlass, high-performance memory subsystem design
Responsibilities
Define and architect high-performance blocks for next-generation networking ASICs; Perform micro-architecture and RTL logic design to maximize throughput while optimizing power efficiency; Partner with the verification team to develop test plans and debug functional issues; Collaborate with the physical design team to define timing constraints, analyze timing violations, and implement timing closure solutions
Seniority
Senior, hands-on IC
