Sr Staff Engineer, Synthesis and STA
Core
Own RTL-to-Gate conversion, constraint development, and timing closure to deliver high-performance, low-power chips.
Role type
Senior Staff IC backend design engineer (synthesis and STA)
Builds
Optimized gate-level netlists and timing-closed silicon for automotive, industrial, infrastructure, and IoT SoCs/MCUs
Domain
Semiconductor design (Digital IC, Physical Design, EDA)
Deliverable
production ML models | product features | dashboards & analysis | research | client delivery | infrastructure | physical/clinical work -> physical/clinical work (Note: This is a hardware design role, mapping to 'physical' work in the context of chip design, but strictly following the allowed list, 'product features' or 'infrastructure' might be misleading. However, the prompt's allowed list for Deliverable is fixed: 'production ML models | product features | dashboards & analysis | research | client delivery | infrastructure | physical/clinical work'. None fit perfectly for 'chip design'. 'Infrastructure' usually means cloud/infra. 'Product features' implies software. 'Physical/clinical work' implies hardware/medical. Given the options, 'physical/clinical work' is the closest semantic bucket for hardware engineering, though imperfect. Let's re-evaluate. The prompt says 'physical/clinical work'. This role is about designing physical chips. I will map it to 'physical/clinical work' as it is the only one involving physical hardware design, or perhaps 'product features' if considering the chip as a product feature. Actually, looking at the list again, none are perfect. But 'physical/clinical work' is the standard fallback for hardware roles in this specific schema if 'hardware' isn't an option. Wait, the prompt says 'physical/clinical work'. I will use 'physical/clinical work' as it covers physical hardware design.
Required skills
Static Timing Analysis (STA), Logic Synthesis, PPA optimization, Tcl/Python/Perl scripting, EDA tool expertise (Fusion Compiler, Innovus, Primetime, Tempus, VCLP, LEC), UPF management, Multi-mode Multi-corner (MMMC) analysis, Formal Verification (LEC), Clock tree synthesis, Constraint development (SDC/UPF)
Preferred skills
Mentoring junior engineers
Technologies
Fusion Compiler, Innovus, Primetime, Tempus, VCLP, LEC, SystemVerilog, SDC, UPF
Responsibilities
Execute hierarchical and physical-aware synthesis flows to translate RTL to gate-level netlists; Perform block-level and full-chip STA across MMMC scenarios; Develop and manage comprehensive timing and power constraints (SDC/UPF); Optimize clock trees and resolve timing bottlenecks; Automate design flows using scripting languages to reduce TAT.
Seniority
Senior Staff, hands-on IC
