Senior Static Timing Analysis Methodology Lead Engineer / Technical Lead
Core
Technical lead for Static Timing Analysis (STA) flows and timing modeling methodology across ASIC, Custom, and Semi-Custom IP designs, bridging design teams and EDA vendors.
Role type
Senior IC Technical Lead (Design Automation)
Builds
Production-grade STA flows, timing sign-off environments, and timing models for FPGA and ASIC designs.
Domain
Semiconductor Design Automation (EDA), Static Timing Analysis, IC Design
Deliverable
production ML models | product features | dashboards & analysis | infrastructure
Required skills
Static Timing Analysis (STA), timing sign-off methodology, SPICE circuit simulation, cell characterization, Python/Tcl scripting, flow architecture, regression infrastructure, cross-functional technical leadership, tape-out support
Preferred skills
Multi-corner multi-mode (MCMM) analysis, Liberty model generation, FPGA timing models, timing reliability/derating, advanced-node timing challenges, AI/ML in design automation
Technologies
Python, Tcl, SPICE, EDA tools (Synopsys/Cadence implied), Shell scripting
Responsibilities
Develop and release production-grade STA flows and automation; mentor engineers on timing methodology; partner with design teams to define requirements and resolve timing issues; evaluate EDA vendor capabilities and drive roadmap escalations; support tape-outs and debug timing issues.
Seniority
Senior, hands-on IC with technical leadership
