Timing Engineer
Core
Lead timing activities for FPGA subsystems, achieving timing convergence from implementation through final sign-off.
Role type
Senior IC timing engineer (FPGA/ASIC)
Builds
High-quality FPGA products for AI, cloud, networking, and edge markets
Domain
Semiconductor hardware design (FPGA/ASIC)
Deliverable
production ML models | product features
Required skills
Static timing analysis (STA), timing constraints, timing closure methodologies, multi-corner/multi-mode (MCMM) analysis, clock planning, automation/scripting (Tcl, Python, Perl), root cause analysis
Preferred skills
Hierarchical timing budgets, clock tree synthesis (CTS), clock architecture optimization, large-scale design automation
Technologies
Cadence Tempus, Synopsys PrimeTime
Responsibilities
Drive timing closure at block and sub-system levels; Develop timing methodologies via flow/scripting; Define and manage I/O timing budgets; Apply advanced sign-off methodologies (POCV, PVT); Generate and validate timing ECOs; Manage large-scale STA runs with automation; Provide actionable timing feedback and ECO guidance
Seniority
Senior, hands-on IC
