Staff Analog Design Engineer, TX/RX Datapath
Core
Own transistor-level design of high-speed SerDes transmit and receive datapath blocks for IO chiplets, driving designs from specification through silicon characterization.
Role type
Staff Analog Design Engineer (SerDes Datapath)
Builds
High-speed SerDes transmit/receive blocks and equalization paths for inference accelerator interconnects.
Domain
Semiconductor hardware design, high-speed analog/mixed-signal circuits, SerDes PHY.
Deliverable
production ML models | product features | infrastructure
Required skills
Transistor-level analog circuit design, SerDes datapath ownership, high-speed driver/receive front-end design, equalization architecture (DFE/FFE), jitter and noise analysis, advanced process node design (FinFET/GAA), silicon bring-up and bench debug, link/channel modeling.
Preferred skills
Die-to-die interconnect experience (UCIe, BoW), PAM4 signaling and DSP-based receiver architectures, familiarity with UCIe/OIF/IEEE/PCIe standards, cross-node porting experience, IBIS-AMI model generation.
Technologies
Cadence Virtuoso, Spectre, MATLAB, Python, S-parameter models, BERTs, oscilloscopes.
Responsibilities
Design output drivers, pre-drivers, serializers, termination networks, CTLE, VGAs, and samplers; derive block-level specs from link budgets; build verification environments with PVT/Monte Carlo coverage; perform link and channel modeling; drive layout co-design with package/signal-integrity engineers; execute silicon bring-up and correlate measurements with simulation.
Seniority
Staff, hands-on IC with deep technical ownership and cross-team influence.