Senior Staff Silicon Physical Design
Core
Developing cutting-edge multi-core in-memory compute SoCs from RTL to GDS.
Role type
Senior Staff Silicon Physical Design Engineer
Builds
Multi-core in-memory compute SoCs
Domain
Semiconductor / ASIC Physical Design
Deliverable
production ML models
Required skills
ASIC Physical Design (RTL to GDS), Synthesis, Floorplanning, Place and Route, Timing Analysis, Physical Verification, Clock Tree Synthesis (CTS), IP Integration, EDA Tools (Primetime, StarRC, Genus, Innovus, Design Compiler, ICC/ICC2, FC, Calibre), Scripting (Python, Tcl, Bash)
Preferred skills
Chip-package-board co-simulation, Packaging knowledge, EDA vendor tool resolution, Semiconductor device physics, Multi-domain design
Technologies
Primetime, StarRC, Genus, Innovus, Design Compiler, ICC/ICC2, FC, Calibre, Python, Tcl, Bash
Responsibilities
Perform synthesis, floorplanning, place and route, extraction, timing analysis, and physical verification. Execute clock tree synthesis (CTS) and custom clock-building techniques. Integrate IPs including memories, I/Os, embedded processors, DDR, and networking fabrics. Develop automation scripts and contribute to flow development. Debug and solve technical challenges related to physical design.
Seniority
Senior Staff, hands-on IC
