Physical Design Engineer - Static Timing Analysis, Annapurna Labs, Cloud Scale Machine Learning
Core
Design and optimization of hardware for data centers, specifically focusing on machine learning inference products like AWS Inferentia.
Role type
Senior IC physical design engineer (static timing analysis)
Builds
AWS Inferentia and other cloud-scale machine learning inference chips
Domain
Semiconductor / ASIC Physical Design / Cloud Infrastructure
Deliverable
production ML models
Required skills
Static Timing Analysis (STA), timing constraint development, EDA tools (PrimeTime, Tempus), ASIC Physical Design (RTL-to-GDSII), scripting (Tcl, Perl, Python), sign-off activities (IR/EM, physical verification, DFT)
Preferred skills
ECO flows (PT-DMSA, Tempus-ECO), advanced nodes (16nm or below), parasitic extraction (STAR-RC, Quantus), circuit level analysis (SPICE, SPECTRE), IO interface timing (DDR, HBM, PCIe)
Technologies
PrimeTime, Tempus, STAR-RC, Quantus, SPICE, SPECTRE
Responsibilities
Develop and maintain flows for block and full-chip level static timing analysis; Write, debug, and validate timing constraints; Run Static Timing Analysis and provide feedback; Provide guidance on fixing timing issues (generate ECOs, fix constraint issues); Develop scripts to automate running timing analysis and generate reports
Seniority
Senior, hands-on IC
