Principal Die-to-Die Interconnect Modeling Architect
Core
Lead a technical team in building and evolving a foundational modeling platform for die-to-die (D2D) PHYs designs, focusing on communication theory, algorithm development, system-level modeling, and architectural verification.
Role type
Principal Die-to-Die Interconnect Modeling Architect
Builds
Foundational modeling platform for D2D PHYs designs
Domain
Semiconductor / High-speed SerDes / Die-to-Die Communication
Deliverable
production ML models
Required skills
Communication theory, Equalization, Adaptive algorithms, System-level modeling, Architectural verification, Silicon correlation, Statistical analysis, MATLAB, Python, SystemC
Preferred skills
UCIe, Advanced packaging (silicon interposers, EMIB, hybrid bonding), Management experience
Technologies
MATLAB, Python, SystemC, Verilog
Responsibilities
Develop behavioral and architectural models to predict link behavior; Perform evaluation and tradeoff analysis of signaling schemes and hardware architecture; Lead algorithm verification of Verilog implementations and Monte Carlo evaluations; Drive correlation between behavioral models, RTL simulation, and production silicon; Provide technical leadership across architecture, analog, digital, and verification teams.
Seniority
Principal, hands-on IC with team leadership
