SoC Interconnect Technology Team Lead
Core
Lead architecture, design, and execution of next-generation coherent and non-coherent interconnect solutions for advanced SoCs, focusing on performance, power efficiency, and system-level optimization.
Role type
Senior IC SoC Interconnect Technology Team Lead
Builds
Robust interconnect IP and future SoC architectures
Domain
Semiconductor / SoC Architecture / Interconnect Fabrics
Deliverable
production ML models | product features | infrastructure
Required skills
SoC architecture and design, coherent interconnect protocols (AMBA ACE, CHI, CCIX, CXL), non-coherent interconnects (AXI, NoC), performance modeling and analysis, cache coherency and memory hierarchy, cross-functional team leadership, tape-out delivery
Preferred skills
Battery-optimized SoC design (low power, DVFS), AI/ML accelerators and heterogeneous compute systems, NoC design methodologies, silicon bring-up and post-silicon validation
Technologies
AMBA AXI/ACE/CHI, CCIX, CXL, NoC
Responsibilities
Lead architecture and development of coherent and non-coherent interconnect fabrics; Define and drive system-level interconnect strategies including topology, QoS, latency, bandwidth, and power optimization; Collaborate with CPU, GPU, NPU, memory, and system teams; Drive adoption of industry standards; Own performance modeling, analysis, and bottleneck identification; Guide microarchitecture, RTL design, and verification strategy; Lead debug and root-cause analysis of complex system-level issues; Mentor and grow a team of architects and engineers; Contribute to roadmap planning for next-generation SoC interconnect technologies
Seniority
Senior, hands-on IC with team leadership
